With the development of integrated circuits, the size of a semiconductor device is becoming increasingly smaller, and it is a trend of mainstream in the semiconductor industry to integrate more devices on a smaller chip.
In a 3D integrated circuit, it is necessary to make a connection or interconnection between semiconductor chips, and for increasingly smaller chips, the process of interconnecting chips becomes difficult. A conventional process of interconnecting chips is generally performed in such a manner: firstly, as shown in FIG. 1, a silicon via 200 is formed in the upper surface of a semiconductor chip 100 on which a semiconductor device 300 may be already formed; the silicon via is then connected with the semiconductor device 300 or local interconnection of the semiconductor device 300 by an interconnecting structure 400; then, as shown in FIG. 2, the semiconductor chip 100 as a whole is flipped, and the lower surface thereof is thinned by grinding to expose the silicon via 200; finally, an interconnection may be performed between the exposed silicon via and silicon vias of other chips so as to accomplish the interconnection between chips.
The use of such a process usually needs to thin the semiconductor chip to a thickness below 150 μm, which brings about severe requirements for both the process and the cost.
In view of this, it is necessary to provide a new semiconductor structure and a method for manufacturing the same to simplify the process flow and save the cost.